With the development of integrated circuit technology, the feature size of semiconductor devices is getting smaller and smaller. Current complementary metal-oxide semiconductor (CMOS) devices use a high dielectric-constant (high-k) material as the gate dielectric layer and a metal as the gate electrode (HKMG). However, the reduction of the size of MOS semiconductor devices brings many problems.
One problem is that the use of silicon dioxide as a gate dielectric layer generates a high gate leakage current due to the tunneling effect. In the case of the same equivalent oxide thickness (EOT) a high-k (high dielectric constant) dielectric material has a physical thickness larger than that of a conventional silicon dioxide, thus, a high-k dielectric material is utilized as a gate dielectric layer to reduce the gate leakage current.
Another problem is that the depletion effect of a polysilicon gate and the finite inversion layer capacitance reduce the EOT, thereby degrading the device performance. Thus, a metal gate electrode is used instead of a polysilicon gate to reduce the depletion effect of the polysilicon gate.
In a conventional high-k dielectric last and metal gate last process, trenches for the gates are formed after removing the dummy gates and dummy gate oxide layers. Next, an interface layer (IL) and a high-k dielectric layer are sequentially formed in the trenches. Thereafter, a work function adjustment layer and a metal electrode material layer are sequentially deposited in the trench. A planarization (chemical mechanical polishing) process is then performed on the metal electrode material layer to form a metal electrode.
A bottom anti-reflective coating (BARC) layer has good trench filling capability and can provide a flat surface thanks to its liquid-like properties, thus a BARC layer is widely used in the metal gate last forming process. In the prior art, the BARC layer is formed after forming the high-k dielectric layer and a PMOS work function adjustment layer in the trench, and a photoresist is then formed on the BARC layer. However, the use of dry etching in the BARC layer removal may cause damage to the high-k dielectric layer below the BARC layer, resulting in plasma induced damage (PID) and bulk traps in the high-k dielectric layer. Bulk traps can reduce the high-k dielectric layer reliability, e.g., positive bias temperature instability (PBTI), time dependent dielectric breakdown (TDDB), and other properties.
FIGS. 1A to 1F are cross-sectional views illustrating intermediate stages of a semiconductor device in a conventional manufacturing method as known in the prior art.
Referring to FIG. 1A, a substrate 11 is provided, and an interlayer dielectric layer 12 having two trenches is formed on substrate 11. The two trenches may be formed with a part of a gate-last process. For example, dummy gates and dummy gate oxide layers are first formed, then an interlayer dielectric layer is then formed to separate the dummy gates, and a planarization process is performed on the interlayer dielectric layer. Thereafter, the dummy gates and the dummy gate oxide layers are removed to form the two trenches.
In the subsequent steps, a gate structure of an NMOS device ad a gate structure of a PMOS device are formed in the two trenches, respectively.
Referring to FIG. 1A, an interface layer 101 is formed at the bottom of the trenches, a high-k dielectric layer 102, a cap layer 103, and a silicon cap layer (Si-cap layer) 104 are sequentially formed on interface layer 101 and sidewalls of the trenches.
Thereafter, referring to FIG. 1B, a thermal annealing may be performed to improve the performance of interface layer 101 and high-k dielectric layer 102. Silicon cap layer 104 is then removed by wet etching or a combination of dry etching and wet etching using cap layer 103 as an etch stop layer.
Next, referring to FIG. 1C, a PMOS work function adjustment layer 105 is formed in the trenches. A BARC layer 106 is then formed filling the trenches, and a photoresist 107 is formed on BARC layer 106.
Next, referring to FIG. 1D, photoresist 107 is patterned to expose the trench of the NMOS device. The BARC layer portion exposed in the trench of the NMOS device is then removed by dry etching. During the dry etching process, plasma bombardment (as indicated by the arrows) may cause damage to high-k dielectric layer 102.
Next, referring to FIG. 1E, photoresist 107 on the trench of the PMOS device is removed, and then PMOS work function layer 105 in the trench of the NMOS device is removed. Thereafter, BARC layer 106 in the trench of the PMOS device is removed by dry etching. During the dry etching process, plasma bombardment may further cause damage to high-k dielectric layer 102 in the trench of the NMOS device and to high-k dielectric layer 102 in the trench of the PMOS device.
Thereafter, referring to FIG. 1F, an NMOS work function adjustment layer 108 and a metal electrode layer 109 are subsequently formed in the trenches.
As described above, the removal of the BARC layer by dry etching may cause damage to the high-k dielectric layer and degrade the reliability of the high-k dielectric layer, thereby adversely affecting the device performance.